(1) Field of the Invention
The invention relates to an automated design methodology and, more particularly, to a method to generate antenna effect models for standard library components for use by automatic placement and routing software.
(2) Description of the Prior Art
Integrated circuits are typically fabricated using a plurality of layers comprising different materials. These layers are formed or deposited using a variety of different processes. Frequently, these deposited layers must be further patterned to form final designs. This patterning is performed using etching processes. A particular etching process of importance in the present invention is plasma etching.
Plasma etching processes comprise a gas ion plasma that is used to etch an exposed layer on an integrated circuit. These plasma etching processes may exhibit high selectivity as well as fine direction control (anisotropy). A well known problem with plasma etching, however, is film charging. In film charging, metal or polysilicon films can become charged by the plasma. This charging is thought to be caused by non-uniformity in the plasma. The accumulation of charge can cause a large voltage potential to develop in the film. Further, the amount of charging is proportional to the exposed area of the film and is, therefore, called the antenna effect.
Referring now to FIG. 1, a cross section of a partially completed integrated circuit device is shown. In this simplified example, a MOS transistor has been formed in substrate 10. The MOS gate 18 is coupled to a metal layer 42. During a plasma etching process 46, charging 50 occurs in the metal layer film 42. The charge 50 on the metal film 42 is effectively coupled to the polysilicon gate electrode 26 of the MOS transistor. If the presence of the charge 50 induces a large voltage difference between the gate electrode 26 and the substrate 10, then this voltage must be sustained over the relatively thin gate oxide layer 22. In a sub-micron process, the gate oxide layer 22 may be in the range of about 40 Angstroms. The large voltage caused by the plasma-induced charging of the metal film 42 appears as an electrical overstress (EOS) or electrostatic discharge (ESD) event 30 to the gate oxide layer 22. It is found that the plasma-induced charging can cause gate oxide 22 failures.
Referring now to FIG. 2, several layers of an integrated circuit device are shown in a very simplified cross section. In the cross section, two gates, GATE170 and GATE272 and two diffusion regions, DIFFUSION174 AND DIFFUSION276, are shown. Metal lines are formed in two metal layers comprising METAL1 (M1) and METAL2 (M2). Contacts 80 are used to couple M1 lines 84, 86, and 88, to the underlying gates and diffusions 70, 72, 74, and 76. Vias 90 are used to couple M1 lines to overlying M2 lines 94 and 96. Interconnect paths are thereby formed using the two metal levels M1 and M2.
As discussed above, the magnitude of charge coupled onto a metal line is proportional to the area of that metal line according to the antenna effect. For example, the antenna effect for the M1 line 84 coupled to GATE170 is proportional to the area of the M1 line 84. Note that GATE170 is electrically coupled to GATE272 using a routing of a contact 70, M184, a via 90, M294, another via 90, M186, and contact 80. This routing could also have been achieved by simply routing from GATE170 to GATE272 using only the M1 line 84. Note, however, that this would increase the total area of M1 coupled directly to GATE170 and GATE272. Therefore, the antenna effect for a proposed M1 line coupling directly between GATE170 and GATE272 would have a greater antenna effect during M1 plasma exposure than the more complex routing shown. It is well known in the art that the antenna effect value for a given routing can be reduced by distributing the routing between several metal layers as shown.
In addition to coupling the gates 70 and 72, the illustrated section shows additional couplings to diffusion regions 74 and 76. These diffusion regions may comprise, for example, source and drain regions of MOS transistors. For example, DIFFUSION174 AND DIFFUSION276 may comprise the drains of NMOS and PMOS transistors. In a complex logic function, such drains are often further coupled to gates such as GATE170 and GATE272 by metal routings. The presence of diffusion regions coupled to the metal lines has a large effect on the plasma charging problem. For example, if plasma charging occurs on the M186, the DIFFUSION2 region 76 can shunt charge through the substrate. This will effectively clamp the voltage across GATE272 and can prevent EOS or ESD damage to this gate. The effect of diffusion regions in reducing plasma-induced ESD has been well demonstrated in the art.
The tradeoff between metal line routing and the presence of diffusion regions has been characterized in the art. Layout rules and design rule checks (DRC) have been implemented to insure that potential plasma-induced ESD damage is avoided. In particular, an antenna ratio may be calculated for any metal line routing. The antenna ratio is defined as the metal line, sidewall area divided by the gate area coupled to that metal line. For example, the M1 line 84 coupled to GATE170 has a sidewall area defined by 2×line length×M1 thickness. The area of GATE170 is defined by gate length×gate width. Therefore, it is relatively straightforward to calculate the antenna effect ratio for M184. This antenna effect ratio can then be compared to a limiting value that has been developed for the process. If the calculated antenna effect ratio exceeds the allowable limit, then the signal needs to be re-routed. For example, part of the routing may need to be moved to M2 to reduce the M1 sidewall area as discussed above.
The effect of diffusion regions coupled to the metal line is taken into account by increasing the allowable limit. For example, the M1 line 86 is coupled to GATE272 and to DIFFUSION174. The antenna ratio is calculated by dividing the sidewall area of M186 by the area of GATE272. The allowable limit for the antenna ratio is then increased to account for this diffusion, or diode, area attached to the metal line. The limit is therefore given by:LIMIT+K×diode area, where LIMIT is the standard antenna effect limit without any diffusions. It is well-known in the art that the antenna effect can be reduced by the presence of diffusion regions. Typically the diode area is nulled if it is smaller than a specified area.
Referring now to FIG. 3, an integrated circuit design architecture is shown. This architecture illustrates a standard cell-based design methodology. In this methodology, a variety of needed standard circuit sub-blocks or standard cells are held in libraries 104. These standard cells are laid out using a custom layout editor 100. The standard cell libraries 104, such as core logic or input output (IO) are checked using a design rule check (DRC) program 130 to insure that they are free from any rule violations regarding layer sizes, spacings, overlap, etc. The antenna effect rule may also be checked for each of these library 104 components using the DRC step 130. After the standard cells pass the DRC process 130, they are released to the library 104 for use.
An automatic placement program is used to place these standard cell components from the libraries 104 into a working IC layout. After placement, an automatic router program 120 is used to route metal lines between the standard cells to complete the design in accordance with the chip-level, circuit netlist. The automatic router 120 generates block/soft IP layout 124 routings as well as chip-level routings 128. These routings are then checked using the DRC program 130. These routed layouts must pass the DRC program 130 to be released for mask design.
The auto-router program 120 can use library antenna models 112 and the process antenna rule 116 to guide the routing process. That is, the router program 120 proposes signal routings to couple the pre-placed standard cells as directed by the netlist. Each proposed routing is then checked against the process, antenna effect rule 116 that has been established for the IC technology that will be used to fabricate the device. This process rule 116 comprises the equations used to generate the antenna effect ratio and ratio limit as described above. The library antenna models 112 allow some limited information regarding the standard library cells 104 to be included in the process rule calculation performed by the auto-router. In this architecture, the auto-router program 120 attempts to find routings that implement the netlist and that will pass the DRC check 130. If the auto-router 120 generated layout does not pass the DRC check 130, it must be re-done.
Referring now to FIG. 4, an exemplary chip layout is shown. This integrated circuit device 300 comprises a number of different types of circuit blocks. An input/output (IO) block 204 comprises a plurality of I/O pads and supporting circuit devices. Several additional blocks make up the core, including a RISC block 208, a hard IP block 212, a PLL 214, Block 1220, Block 2224, and a glue logic block 216. Each of these blocks may be generated using a plurality of standard cells that are placed and routed as described above. At this level of the layout process, however, it assumed that the various blocks may be treated as components from the library as described in FIG. 3.
Referring again to FIG. 4, the automatic place and route software arranges the various blocks shown to optimize the layout and then begins to route signal lines 232 between the various blocks as defined by the design netlist. As the signal routing 232 is made from a cell pin 228 of one block to a cell pin 228 of another block, the routing software can calculate the antenna effect ratio for the routing and verify that the ratio does not exceed the specified limit. However, the calculation that can be performed by the router is severely limited because the routing program has very limited information on the contents of the blocks that are being routed. For example, the gate area and source/drain area coupled to the pin 228 may be extracted from a SPICE netlist of the block. However, the netlist contains no information on the metal routings 236 used within the block. Further, no information is available to the router regarding which metal level, or levels, are coupled to these gate and source/drain areas.
Referring now to FIG. 5, an example of the interface between a block 250 and the chip-level 248 is shown in cross section. As can be seen, the chip-level 248 routing information necessary for evaluation of the antenna effect at pin A is visible to the routing program. In particular, the routing program can evaluate the gate area due to GATE(1) 251, the absence of a diffusion area, and the areas of M1261, M2271, and M3281. However, the routing program has no visibility regarding the antenna effect information within the block 250. The routing program may use the netlist to conclude that GATE(2), GATE(3), GATE(4), DIFF(1), and DIFF(2) are coupled to pin A. However, the router cannot know the complex arrangement of metal layers M1, M2, M3, and M4, used within the block.
Referring again to FIG. 3, the routing program 120 attempts to generate a routing layout that will pass the antenna effect checking in the DRC program 130. However, as has been described above, the routing program 120 has limited information on the internal contents of the blocks that it is routing. Therefore, the routing program 120 can easily create a routing that appears to meet the antenna effect requirements during the routing analysis but that fails the final DRC check 130. If this happens, the time consuming routing process must be repeated. This process of routing and DRC checking may require several, time consuming iterations or human interventions to complete.
To avoid the iteration process, the designer is tempted to use very conservative models 112 for the block pins. In other words, a worst case internal metal area is assumed for each pin. This approach can help to prevent final DRC failures of completed routing due to antenna effect violations. However, by using a very conservative model, that may be completely too conservative for many of the block pins, the routing program is forced to work very hard to find “bullet proof” routes for every inter-block routing so that the DRC is certain to pass it. This causes unacceptably long routing program times. In addition, the routing program will sometimes fail to find any acceptable routing that will fix all of the antenna violations that the too conservative model causes. A means of providing a more accurate model of the antenna effect parameters pertinent to the block pins would eliminate these routing problems.
Several prior art inventions relate to plasma-induced, ESD due to the antenna effect. U.S. Pat. No. 6,308,308 B1 to Cronin, III et al, and U.S. Pat. No. 5,966,517 to Cronin, III et al teach a method to prevent plasma-induced, ESD damage in a standard cell based IC. Placeholders for antenna diodes are designed into each standard cell input. After placement and routing, a determination is made as to where antenna diodes are needed in the standard cells for ESD protection. The antenna diode placeholders are replaced at these locations with real diodes. U.S. Pat. No. 6,292,927 B1 to Gopisetty et al discloses a method to optimally select the best discharge paths for metal lines to reduce plasma-induced charging.